In video systems, the information displayed is segmented into discrete elements referred to as "pixels", the number of pixels per unit area determining the available resolution. Each of these pixels for a simple black and white system can be defined in terms of one bit of data; whereas, a more complex system utilizing pixels having differing colors and intensity levels requires significantly more bits of data. To display the pixel information stored in memory, data is read from memory and then organized in an interim storage medium in a serial format. As each horizontal line in the display is scanned, the pixel data is serially output and converted to video information. For example, the stored data for each black and white pixel correspond to a predetermined position in the scan line and determines the video output for either a "white" level or a "black" level. The serial formatting of pixel data is described in U.S. Pat. No. 4,322,635, issued to Redwine, U.S. Pat. No. 4,347,587, issued to Rao and U.S. patent application Ser. No. 567,040 filed on Dec. 30, 1983, all assigned to Texas Instruments Incorporated.
In designing a video memory, two of the primary constraints facing the designer are the number of pixels required per scan line and the scanning rate. This determines how the pixel information is mapped into the memory and the rate at which the stored pixel information must be accessed and serially output. Typically, video memories are "pixel mapped" such that one row of memory elements or portion thereof directly corresponds to the pixel information of a given scan line or portion thereof. For example, in a black and white system having 256 pixels per scan line, a memory having 256 memory elements per row would be utilized. The information in the row is accessed and stored in a serial shift register for serial output therefrom during a given scan line, thereby requiring only one memory access per scan line. While data is being output from the serial shift register to the display, data is being accessed from the memory for updating of display data. This data is transferred to the shift register during the retrace period between adjacent scan lines. Therefore, the number of rows and columns of memory elements is determined by the number of pixels per scan line, the number of bits of information per pixel and the number of scan lines in the display. The operation of the serial shift register is described in more detail in U.S. Pat. Nos. 4,322,635 and 4,347,587, with a typical bit mapped video memory described in U.S. patent application Ser. No. 567,040.
In applications utilizing pixel mapped video memories, a large number of individual memories are arranged in arrays such that a single access operation outputs a predetermined pixel pattern. This allows a large number of pixels and/or bits per pixel to be output during a single access time, thereby reducing the time required to access a given set of information. This array configuration may require the shift registers associated with individual memories to be either cascaded or arranged in parallel.
To facilitate the use of multiple pixel mapped video memories, it is desirable to incorporate more than one memory on a single semiconductor chip. To provide a viable device from both an economical and a marketing standpoint, each of the integrated memories must maintain some degree of independent operation relative to the other memories on the same chip and yet share as many control functions as possible. This is necessary to reduce the number of integrated circuit pins required to interface between the peripheral circuitry and the chip itself and also to reduce the circuit density. When multiple pixel mapped video memories are integrated onto a single semiconductor chip, it is desirable to have independent access to the serial inputs and outputs of each of the memories and also to have independent control of the random Read/Write modes for the memories. This would require separate serial-in and serial-out interface pins for each memory, in addition to separate pins for the Read/Write control functions, resulting in an impractical multi-pin package. Additionally, the control circuitry required to provide the various independent functions would increase the density of the chip circuitry.
In view of the above disadvantages with integrated multiple memory semiconductor chips, it is desirable to provide a multiple memory chip having shared control functions utilizing a minimum chamber of pins to interface with peripheral circuitry, yet retaining a high degree of independent control of each of the memories in a given chip.